1. Field of the Invention
Embodiments of the invention generally relate to a method and apparatus for cleaning an at least partially exposed copper layer disposed on a substrate.
2. Background of the Related Art
Sub-quarter micron, multi-level metallization is a key technology for the next generation of ultra large scale integration (ULSI). This technology utilizes interconnect features, for example, contacts, vias and lines, that are formed by planarization of films formed in high aspect ratio apertures. Reliable formation of these interconnect features is important to the success of the next generation of ULSI, and to a continued effort to increase circuit density and quality on individual substrates and die.
The increase in circuit density primarily results from a decrease in the widths of interconnect features such as vias, contacts and other features, as well as from a decrease in the thickness of dielectric materials disposed between these interconnect features. Typically, cleaning the apertures to remove contaminants prior to metallization is required to improve device integrity and performance. The decrease in width of the apertures results in larger aspect ratios for the apertures and increased difficulty in cleaning the apertures prior to filling the apertures with metal or other materials. Failure to clean the apertures can result in void formation within the apertures or an increase in the resistance of the interconnect features. Therefore, there is a great amount of ongoing effort being directed at cleaning small apertures having high aspect ratios, especially where the ratio of feature height to width is 3:1 or larger.
The presence of native oxides and other contaminants such as etch residue within a small apertures are problematic because they contribute to void formation during metallization by promoting uneven distribution of a depositing material such as metal. Regions of increased growth can merge and seal the small apertures before regions of slower growth can be filled with the depositing metal. It is known that native oxides form within the apertures when a portion of a layer (or sublayer), such as silicon, aluminum, or copper, is exposed to oxygen in the atmosphere or is damaged during a plasma etch step. Other contaminants within the apertures can be sputtered material from an oxide over-etch, residual photoresist from a stripping process, leftover polymer from a previous oxide etch step, or redeposited material from a sputter etch process.
The presence of native oxides and other contaminants is also problematic because they can reduce the electromigration resistance of vias and small apertures. The contaminants can diffuse into a dielectric layer, a sublayer, or a deposited metal and alter the performance of devices that include the small features. Even if contamination is limited to a thin boundary region within the features, the thin boundary region is a substantial part of the small features. An acceptable level of contaminants in the features decreases as the features get smaller in width.
Pre-cleaning of features to remove native oxides and other contaminants has become increasingly utilized to prepare surfaces for barrier layer or metal deposition. Conventional pre-clean processes typically include a plasma etch to remove contaminants and expose native oxides. The native oxides may then be removed by an etching process or removed using a reduction reaction. However, when used to pre-clean copper, conventional pre-clean processes typically result in sputtered or etched copper from an underlying layer being deposited on sidewalls of an apertures. The deposited copper is generally in the form of agglomerated copper particles that create an uneven and rough sidewall surface which adversely effects subsequent depositions. In particular, the agglomerated copper causes void formation, thereby contributing to device defects and defective substrates.
Additionally, conventional pre-cleaning processes typically operate at substrate temperatures between about 250 to about 300 degrees Celsius. At these temperatures, low-k materials utilized during the fabrication of some devices is at or near its glass transitions temperature, and can contribute to poor adhesion or delamination of the low-k material and the underlying layer. Moreover, high substrate temperatures during pre-cleaning may contribute to device damage induced by gate charging and fluorine radical outgassing from exposed SOG in via sidewalls. The heated SOG are more apt to outgas at increased temperatures and may react with barrier and seed layers within the via, causing delamination and poor barrier properties.
Therefore, there is a need for an improved method and apparatus for pre-cleaning a substrate.